Rupendra Kumar Sharma, Ph. D.

Assistant Professor

místnost: T2:B3-139
telefon: +420 2 2435 2167
email: sharmrup@fel.cvut.cz

Current Activities

  • 12/21–Present      Assistant Professor, Department of Electrotechnology, Faculty of Electrical Engineering, Czech Technical University in Prague, “the experimental preparation of various materials by Pulse Laser Deposition (PLD) for advanced silicon solar cell technology”.
  • 10/20–11/21        Postdoctoral Fellow (with Prof. Jakub Holovsky) Czech Technical University in Prague, “The development of new technology of selective contacts to the silicon absorber based on silicon oxide passivation and metal oxides”.
  • 09/18–12/20        Executive Director, OYO Hotels Netherlands B.V., “Hospitality activity in Amsterdam and surrounding Areas.
  • 10/15–09/20        Managing Director, Indo Western s.r.o., “Education consultancy, professional courses, training and other educational events, including lecturing”.

Research Experience

  • 09/13–09/15        Postdoctoral Fellow (with Prof. Pavel Hazdra) Czech Technical University in Prague, “Silicon carbide-based Power devices and their applications for power savings”
  • 09/14–12/14        Visiting Scholar (with Prof. Philippe Godignon) CNM-CSIC, Campus UAB, Bellaterra, Barcelona, Spain, “Simulation and characterization of irradiated 4H-SiC MOSFETs”
  • 09/11–08/13        Marie-Curie Postdoctoral Fellow (with Prof. Matthias Bucher) Technical University of Crete, Chania Greece, “Compact modelling of nanoscale multi-gate MOSFET and of high-voltage MOSFETs”
  • 07/10–06/11        Postdoctoral Fellow (with Prof. Susanna Reggiani) University of Bologna, Bologna, Italy, “Modeling and characterization of the hot-carrier stress degradation and thermal effects in MOSFET devices for smart power technologies”

Education

  • 08/07–03/10        Ph. D. in Electronics (with Prof. Mridula Gupta), University of Delhi, India, Graduated on the 20th of March 2010, “Two dimensional analytical modeling and simulation of gate misalignment effect in fully depleted double gate MOSFET”
  •  10/05–07/07        Project Fellow (with Prof. R. S. Gupta), University of Delhi, India “Modeling simulation and characterization of modified double gate sub-100 nm MOSFET for ULSI circuit application.”
  •  07/03–06/05        Master in Physics, C. C. S. University, Meerut, India

Teaching Experience

  • 09/12–02/13        Modeling and simulation of nanoscale transistors, Technical University of Crete, Greece
  • 02/14–06/14        Simulation of SiC power devices using TCAD, Silvaco, Czech Technical University in Prague, 100 Hours
  • 02/22–06/22        Photovoltaic: Theory and Applications, Czech Technical University in Prague

Fellowships and Awards

  • Marie-Curie Postdoctoral Fellowship:        Compact Modelling Network (COMON), Funded under 7th Framework Programme, IAPP Marie-Curie Action, European Union, 2011-2013
  • EMMA Postdoctoral Fellowship:                  Erasmus Mundus Action 2 Scholarship (EMMA number: 20110551) European Commission (declined), 2011-2012
  • Individual Research Fellowship:                   Advanced Research Centre for Electronic System (ARCES), University of Bologna, Italy. 2010-2011
  • Senior Research Fellowship:                          Council of Scientific & Industrial Research (CSIR), Human Resource Development Group, India. 2009-2010
  • Junior Research Fellowship:                          Defence Research & Development Organization (DRDO), India, 2005-2009

Technical Skills

  • Preparation of thin films of various conducting oxide using Pulsed laser Deposition (PLD)
  • Modeling of transport problems in the field of solid-state electronics
  • Physical analysis and numerical characterization of CMOS, power devices and solar cells.
  • Ability in the use of ICCAP, MATLAB, Mathcad, Verilog-A.
  • Expertise in CAD software’s for the analysis of electronic devices.

Peer-Reviewer

  • Microelectronics Journal – Elsevier

Citation indices

Citations: 394; h-index: 13, i10-index: 14, https://scholar.google.com/citations?user=r97lNY0AAAAJ

Book 

“Modeling and Simulation of Gate Misalignment Effect in MOSFETs” Scholars’ Press, Heinrich Böcking Str. 68, 66121, Saarbrücken, Germany, ISSN No. 9783639708028, June 2015.

Journal Publications

    1. Maksym Buryi, Katarína Ridzonová , Neda Neykova, Lucie Landová, František Hájek, Vladimir Babin, Katerina Decká, Rupendra Kumar Sharma and Ognen Pop-Georgievski, “Effect of UV Irradiation on the Growth of ZnO:Er Nanorods and Their Intrinsic Defects”, Chemosensors 2023, 11, 156, https://doi.org/10.3390/chemosensors11030156.
    2. K. Sharma, M. Boccard, and J Holovský, “New Metric for Carrier Selective Contacts for Silicon Heterojunction Solar Cells”, Solar Energy Journal, vol. 244, pp. 168-174, August 2022.
    3. Jakub Holovský, Eva Horynová, Lukáš Horák, Katarína Ridzoňová, Zdeněk Remeš, Lucie Landová, and Rupendra Kumar Sharma, “Pulsed Laser Deposition of High-Transparency Molybdenum Oxide Thin Films” Vacuum – Journal, vol. 194, 110613, ISSN: 0042-207X, December 2021.
    4. Nikolaos Makris, Farzan Jazaeri, Jean-Michel Sallese, Rupendra Kumar Sharma, Matthias Bucher, “Charge-based modeling of long-channel symmetric double-gate junction FETs—Part I: Drain current and transconductances” IEEE Transactions on Electron Devices, 65, no. 7, pp. 2744-50, ISSN: 0018-9383, June 2018.
    5. K. Sharma, and M. Bucher, “A comprehensive analysis of nanoscale single and multi-gate MOSFETs “, Microelectronics Journal, vol. 52, pp. 66 – 72, ISSN: 0026-2692, June 2016.
    6. K. Sharma, P. Hazdra, S. Popelka, A. Mihaila and H. Bartolf, “Optimization of 1700V 4H-SiC JBS Diode Parameters”, Materials Science Forum, vol. 858, pp. 782-785, ISSN: 0255-5476, May 2016.
    7. K. Sharma, P. Hazdra, S. Popelka, “Simulation and Characterization of 4H-SiC JBS Diodes Irradiated by Hydrogen and Carbon Ions, vol. 6, no. 2, 2015.
    8. Vobesky, P. Hazdra, S. Popelka, and R. K. Sharma, “Impact of Electron Irradiation on the ON-State Characteristics of 4H-SiC JBS Diode”, IEEE Transactions on Electron Devices, vol. 62, pp. 1964-69, June 2015.
    9. K. Sharma, S. Popelka, P. Hazdra, “The effect of light ion irradiation on 4H-SiC MPS power diode characteristics: Experiment and Simulation” IEEE Transactions on Nuclear Science, vol. 62, no. 2, pp. 534-541, ISSN: 0018-9499, April 2015.
    10. Hazdra, R. K. Sharma, and S. Popelka, “The Effect of Proton and Carbon Irradiation on 4H-SiC 1700V MPS Diode Characteristics”, Materials Science Forum, vols 821-823, pp. 612-615, Jan 2015.
    11. Popelka, P. Hazdra, R. K. Sharma, V. Záhlava, and J. Vobecký, “Effect of Neutron Irradiation on High Voltage 4H-SiC Vertical JFET Characteristics: Characterization and Modeling” IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3030-36, Dec 2014.
    12. Antonopoulos, M. Bucher, K. Papathanasiou, N. Mavredakis, N. Makris, R. K. Sharma, P. Sakalas, and M. Schroter, “Modeling of High Frequency Noise of Silicon CMOS Transistors for
      RFIC Design”, International Journal of Numerical Modelling, vol. 27, pp. 802-811, ISSN:1099-1204, Feb 2014.
    13. Antonopoulos, M. Bucher, K. Papathanasiou, N. Makris, R. K. Sharma, P. Sakalas, and M. Schroter, “CMOS Small Signal and Thermal Noise Modelling upto High Frequencies”, IEEE Transactions on Electron Devices, vol. 60, pp. 3726-33, ISSN: 0018-9383, November 2013.
    14. K. Sharma, and M. Bucher, “Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs”, IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 992-998, ISSN: 1536125X, Sept. 2012.
    15. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise, ” Optimization and Analysis of the Dual N/P-LDMOS Device” IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 745-53, March 2012.
    16. K. Sharma, M. Gupta and R. S. Gupta, ” TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET” IEEE Transactions on Electron Devices, vol. 58, no. 9, pp. 2936-2943, September 2011.
    17. K. Sharma, R. Gupta, M. Gupta and R. S. Gupta, “Dual Material Double Gate SOI n-MOSFET: Gate Misalignment Analysis” IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1284-1291, June 2009.
    18. K. Sharma, R. Gupta, M. Gupta and R. S. Gupta, “Dynamic Performance of Graded Channel DG FD SOI n-MOSFETs for Minimizing the Gate Misalignment Effect” Microelectronics Reliability, vol. 49, pp. 699-706, ISSN: 262714, June 2009.
    19. K. Sharma, M. Gupta and R. S. Gupta, “Two-Dimensional Analytical Subthreshold Model of Graded Channel DG FD SOI n-MOSFET with Gate Misalignment Effect”, Superlattices and Microstructures, vol. 45, no. 3, pp. 91-104, ISSN: 10963677, March 2009.
    20. K. Sharma, R. Gupta, M. Gupta and R. S. Gupta, “Graded Channel Architecture: the Solution for Misaligned DG FD SOI n-MOSFETs”, Semiconductor Science and Technology, vol. 23, no. 7, 075041, ISSN: 0268-1242, July 2008.

International Proceedings/Conferences

    1. K. Sharma, L. Horákc, K. Ridzoňovb and J. Holovský, “High-Transparency Molybdenum Oxide Thin Films: Pulsed Laser Deposition”, 2022 TechConnect World Innovation Conference, Washington DC, USA, June 13-15, 2022.
    2. K. Sharma, M. Boccard, and J Holovský, “Analysis of Silicon Heterojunction Solar Cells under Low Illumination Conditions”, 10th European Conference on Renewable Energy Systems (ECRES 2022), Istanbul, Turkey May 7-9, 2012.
    3. Holovský, A. Peter Amalathas, R. K. Sharma, “Optical and electrical performance of a layer in solar cell in a limit of very low thickness”, The 2021 Spring Meeting of the European Materials Research Society (E-MRS).
    4. Holovský, B. Conrad, L. Antognini, R. K. Sharma, A Peter Amalathas, “Illumination-Dependent Requirements for Heterojunctions and Carrier-Selective Contacts on Silicon”, 11th International Conference on Silicon Photovoltaics (SiliconPV 2021).
    5. K. Sharma, P. Hazdra, S. Popelka, A. Mihaila and H. Bartolf, “Optimization of 1700V 4H-SiC JBS Diode Parameters”, International Conference on Silicon Carbide and Related Materials, Giardini Naxos, Oct 4-9, 2015.
    6. Eric Pertermann, Josef Lutz, K. Sharma, P. Hazdra, S. Popelka, Hans Peter Felsl, Franz-Josef Niedernostheide, and Hans-Joachim Schulze, “Investigation of Deep Levels in SiC-Schottky Diodes with Frequency Resolved Admittance Spectroscopy”, 2015 17th European Conference on Power Electronics and Applications (EPE’15 ECCE-Europe), Sept 8-10, 2015.
    7. K. Sharma, P. Hazdra and S. Popelka, “Simulation and Characterization of Ion Irradiated 4H-SiC JBS Diode”, 22nd International Conference on Mixed Design of Integrated Circuits and Systems, Torun, Poland, Jun 25-27, 2015.
    8. Hazdra, R. K. Sharma, and S. Popelka, “The effect of proton and carbon irradiation on 4H-SiC 1700 V MPS diode characteristics”, European Conference on Silicon Carbide and Related Materials (ECSCRM) Grenoble, France, 21-25 September 2014.
    9. K. Sharma, P. Hazdra and S. Popelka, “The effect of fast ion irradiation on 1700 V 4H-SiC MPS diode: Experimental and Simulation”, The 12th International Seminar on Power Semiconductors (ISPS’14), Prague, August 27-29, 2014.
    10. Popelka, P. Hazdra, R. K. Sharma, V. Záhlava, and J. Vobecký, “Effect of Neutron Irradiation on High Voltage 4H-SiC Vertical JFET Characteristics: Characterization and Modeling”, The Nuclear and Space Radkiation Effects Conference, France, Paris, July 14-18, 2014.
    11. Antonopoulos, M. Bucher, K. Papathanasiou, N. Makris, R. K. Sharma, P. Sakalas, and M. Schroter, “CMOS RF Noise, Scaling, and Compact Modeling for RFIC Design”, Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, Washington, June 2-4, 2013.
    12. K. Sharma, A. Antonopoulos, N. Mavredakis, M. Bucher, “Impact of Design Engineering on RF linearity and Noise Performance of Nanoscale DG SOI MOSFETs”, 14th Int. Conf. on Ultimate Integration of Silicon (ULIS), Warwick, UK, March 19-21, 2013.
    13. Dimakos, M. Bucher, R. K. Sharma, and I. Chlis, “Ultra-Low Voltage Drain-Bulk Connected MOS Transistors in Weak and Moderate Inversion”, IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Spain, 9-12 December 2012.
    14. K. Sharma, and M. Bucher “Analysis of gain transconductance frequency product for advanced MOSFETs”, 5th International Conference on Micro-Nanoelectronics, Nanotechnoligies and MEMs, Heraklion, 7-10 October 2012.
    15. K. Sharma, and M. Bucher “Optimization of the device design technologies for optimum analog/RF performance of Nanoscale DG MOSFETs” Nanotech Conference, Santa Clara, USA, pp. 27-30, June, 18-21, 2012.
    16. K. Sharma, A. Antonopoulos, N. Mavredakis and M. Bucher “Analog/RF Figures of Merit of Advanced DG MOSFETs” 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Mexico, 14-17, March, 2012.
    17. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise “TCAD optimization of a dual N/P–LDMOS transistor” 41st European Solid-State Device Research Conference (ESSDERC)” Finland, 12-16, Sept, 2011.
    18. K. Sharma, M. Gupta and R. S. Gupta, “A Simulated Study of Gate Misalignment Effects on the Dynamic Performance of Nanoscale Double Gate and Dual Material Double Gate SOI n-MOSFET”, 12th International Symposium on Microwave and Optical Technology” (ISMOT) New Delhi, December 16-20, 2009.
    19. K. Sharma, M. Gupta and R. S. Gupta, “High Tolerance to Gate Misalignment in Graded Channel Double Gate SOI n-MOSFETs: Small Signal parameter Analysis”, Asia pacific Microwave Conference, Hong Kong, December 16-20, 2008.
    20. K. Sharma, M. Gupta and R. S. Gupta, “Optimization of the Gate Misalignment Effects in Graded Channel DG FD SOI n-MOSFET with high-k gate dielectrics”, Int. Conference on Recent Advances in Microwave Theory and Applications, Jaipur, November 21 – 24, 2008.
    21. K. Sharma, M. Saxena, M. Gupta and R. S. Gupta, “A 2-D Analytical Subthreshold Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET”, 14th International Workshop on the Physics of Semiconductor Devices (IWPSD) Mumbai, December 16-20, 2007.
    22. K. Sharma, M. Saxena, M. Gupta and R. S. Gupta, “Scrutinize the Gate Misalignment Effects in Graded Channel DG FD SOI n- MOSFET”, 11th International Symposium on Microwave and Optical Technology (ISMOT), Villa Mondragone, Italy, Dec. 17-21 2007.
    23. K. Sharma, M. Saxena, M. Gupta and R. S. Gupta, “A 2-D Analytical Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET”, Indian Microelectronics Society Conference on Trends in VLSI and Embedded System, Chandigarh, Aug. 17-18, 2007.