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 Charge Balance Effects on UIS Performance of Trench MOSFETs

Authors & Affiliations

Zia Hossain, Shengling Deng, Mo Grimaldi
onsemi
5701 N Pima Rd., Scottsdale, AZ 85250

DOI

https://doi.org/10.14311/ISPS.2023.007

Abstract

The Unclamped Inductive Switching (UIS) test is a widely used technique for evaluating the robustness of power MOSFETs under avalanche conditions. The aim of this paper is to optimize the charge balance condition for active and termination cells for optimal UIS performance, characterized by a higher and tighter avalanche current (Iav or Ipk) distribution across the wafer, resulting in a minimum loss in UIS yield during production. The paper investigates the design layout of active and edge termination cells to ensure that avalanche failures occur in the active cell area rather than in the edge termination cell area, which has a weaker UIS capability.

Keywords:

Unclamped Inductive Switching (UIS) test, termination cells

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