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 Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Authors & Affiliations

Ralf Lerner and Nis Hauke Hansen,
Technology – Process Development
X-FAB Global Service GmbH;
Erfurt, Germany

DOI

10.14311/ISPS.2021.015

Abstract

 Several approaches for close integration of power switches with CMOS logic are subject of technical
evaluations and academic discussions. This paper identifies the commercially relevant processing
steps of different integration methods (HV and SOI CMOS, monolithic integration in SOI and in GaN,
Direct Wafer Bonding, micro-Transfer-Printing of GaN on CMOS and CMOS on GaN) and compares
them on simple cost per wafer and cost per chip models. Four examples of real ICs verify the simple
costs per chip model. Commercially attractive high voltage to logic partitionings are identified for the
different integration approaches.

Keywords:

 heterogeneous integration, monolithic integration

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