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 TCAD Simulation of the Bipolar Degradation in SiC MOSFET Power Devices

Authors & Affiliations

 A. Lachichi and P. Mawby,
School of Engineering, University of Warwick.
Coventry, United Kingdom

DOI

10.14311/ISPS.2021.012

Abstract

 Reliability and performance of SiC high power devices are still limited by inherent SiC material defects despite tremendous progress made to reduce the density of these defects. The bipolar degradation remains a major challenge for developing high voltage SiC power devices. It is mainly due to the presence of Shockley-type stacking sequence faults (SFs) within the hexagonal SiC structure lattice, creating 3C-like SiC regions embedded within the main 4H-SiC structure. In this paper, we present a two dimensional numerical model of 4H-SiC power MOSFET device in which the drift region of the device is formed by a 4H-3C-4H heterojunction to account for the bipolar degradation. TCAD simulation results showed that the 3C- nano-layer creates a high resistive layer, effectively preventing the current flows across it, hence reducing the total active area of the device.

Keywords:

 Bipolar degradation, stacking faults, heterojunction, 3C- SiC.

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